1. Field of the Invention
The present invention relates to a multi-phase clock signal generator, a signal phase adjusting loop utilizing the multi-phase clock signal generator, and a multi-phase clock signal generating method, and particularly relates to a multi-phase clock signal generator comprising a ring phase shifting loop, a signal phase adjusting loop utilizing the multi-phase clock signal generator, and a multi-phase clock signal generating method.
2. Description of the Prior Art
A multi-phase clock signal generator is always applied to the electronic apparatus needing clock signals with different phases, such as a DDR (double date rate) ram.
However, the circuit or method for generating multi-phase clock signals always needs huge circuit region or complicated design. For example, a quadrature PLL utilizing a quadrature oscillator may be utilized to generate multi-phase clock signals. However, a frequency of the quadrature oscillator is controlled by voltage and very sensitive to supply voltage noise. Also, a frequency of the quadrature oscillator is not actively driven by external clock frequency and is free running. Also, such structure needs a large circuit region and high power consumption.
Also, an analog multi-phase generator utilizing a delay chain controlled by a charge pump is also utilized to generate multi-phase clock signals. However, such circuit also has huge circuit area and may induce high power consumption. Besides, analog logic is relatively difficult for process portability, sensitivity for high yield in mass production.
Additionally, phase skew problems may exist in the multi-phase clock signals. The phase skew problems are difficult in achieving high accuracy. For example, some prior arts may utilize a plurality of delay lock loops to correct the phase skew issue. However, such structure needs a large circuit size, high power consumption and very complicated control logic. The locking time is too long, which is not appropriate for high speed applications.